In memory circuits there is typically a memory read latency that is the time period it takes for valid data to be read out of a memory circuit. A memory write latency is typically also required that is the time period to hold valid data for a memory circuit to write the data into memory. The memory read latency and the memory write latency may sometimes be buffered from a processor by a cache memory. However, there are occasions when the desired data is not found in the cache memory. In those cases, a processor may need to then read or write data with the memory circuits. Thus, the respective memory read latency or memory write latency may be experienced by the processor. If memory circuits differ, the memory read latencies and memory write latency may be inconsistent from one memory circuit to the next. In which case, the memory read latency and memory write latency experienced by a processor will differ.
Previously, memory modules were plugged into a mother or host printed circuit board and coupled in parallel to a parallel data bus over which parallel data could be read from and written into memory. The parallel data bus had parallel data bit lines that were synchronized together to transfer one or more data bytes or words of data at a time. The parallel data bit lines are typically routed over a distance on a printed circuit board (PCB) from one memory module socket to another. This introduces a first parasitic capacitive load. As the memory modules are plugged into a memory socket, an additional parasitic capacitive load is introduced onto the parallel data bits lines of the parallel data bus. As there may be a number of memory modules plugged in, the additional parasitic capacitive load may be significant and bog down high frequency memory circuits.
One memory module is typically addressed by an address on address lines at a time. The one addressed memory module, typically writes data onto the parallel data bus at a time. Other memory modules typically have to wait to write data onto the parallel data bus in order to avoid collisions.
While parallel data bit lines may speed data flow in certain instances, a parallel data bus in a memory may slow the read and write access of data between a memory circuit and a processor.